1. Field of the Invention
Embodiments of the present disclosure are directed to high density semiconductor devices, such as non-volatile memory, and methods of forming the same.
2. Description of the Related Art
As the size of electronic devices continue to decrease, there is continual pressure to shrink the substrate area required to implement the various integrated circuit functions. Semiconductor memory devices, for example, and the fabrication processes therefor are continuously evolving to meet demands for increases in the amount of digital data that can be stored in a given area of a silicon substrate. Such demands stem from a desire to increase the storage capacity within a memory card while maintaining or even decreasing the card form factor.
Electrical Erasable Programmable Read Only Memory (EEPROM), including flash EEPROM, and Electronically Programmable Read Only Memory (EPROM) are among the most popular non-volatile semiconductor memories. One popular flash EEPROM architecture utilizes a NAND array having a large number of strings of memory cells connected through one or more select transistors between individual bit lines and common source lines. FIG. 1 is a top view showing a single NAND string and FIG. 2 is an equivalent circuit thereof. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104 and 106 in series and sandwiched between a first select gate 120 and a second select gate 122. Select gate 120 connects the NAND string to a bit line via bit line contact 126. Select gate 122 connects the NAND string to a common source line via source line contact 128. Each of the transistors 100, 102, 104 and 106 includes a control gate and a floating gate. For example, transistor 100 has control gate 100CG and floating gate 100FG. Transistor 102 includes control gate 102CG and a floating gate 102FG. Transistor 104 includes control gate 104CG and floating gate 104FG. Transistor 106 includes a control gate 106CG and a floating gate 106FG. Control gate 100CG is connected to word line WL3, control gate 102CG is connected to word line WL2, control gate 104CG is connected to word line WL1, and control gate 106CG is connected to word line WL0.
Although FIGS. 1 and 2 show four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, or more.
The charge storage elements of current flash EEPROM arrays are most commonly electrically conductive floating gates, typically formed from doped polysilicon material. Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. Such a cell is described in an article by Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO”) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable. The cell is erased by injecting hot holes into the nitride. See also Nozaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,” EEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, which describes a similar cell in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.
Memory cells of a typical non-volatile flash array are divided into discrete blocks of cells that are erased together. That is, the block contains the minimum number of cells that are separately erasable together as an erase unit, although more than one block may be erased in a single erasing operation. Each block typically stores one or more pages of data, where a page includes the minimum number of cells that are simultaneously subjected to a data programming and read operation as the basic unit of programming and reading, although more than one page may be programmed or read in a single operation. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system. An example is a sector of 512 bytes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the block in which it is stored.
As demands for higher densities in integrated circuit applications have increased, fabrication processes have evolved to reduce the minimum feature sizes of circuit elements such as the gate and channel regions of transistors. For example, Choi et al., “Sublithographic Nanofabrication Technology for Nanocatalysts and DNA Chips,” J. Vac. Sci. Technol. B 21(6), November/December 2003, pp. 2951-2955, describes an iterative spacer lithography technique which multiplies the pattern density in an integrated circuit to achieve an element length and a corresponding space therebetween that is smaller than a minimum definable lithographic feature size. Such decreases in the sizes of circuit elements, as well as other considerations, increase the need for precision in fabrication processes and integrity in resulting materials.
Known iterative spacer lithography techniques do not address the issue of how to obtain specific desired relative sizes of element length and corresponding spaces between elements in a finished integrated circuit. For example, known iterative spacer technology does not disclose the starting points and steps required to obtain a finished integrated circuit where the element length is equal to the length of the space between elements (or some other desired endpoint length and spacing).
Moreover, known iterative spacer lithography techniques disclose deposition of layers on rounded surfaces formed during the iterative spacer lithography steps. In particular, when the first set of spacers are formed, these spacers have a non-uniform profile; namely, a straight edge formed against the structure on which they are deposited, and a curved edge defined by the etching step by which the spacers are defined. Conventionally, a second spacer layer is formed on the first spacer layer. However, because the first spacer layer has a non-uniform profile (one rounded edge and one straight edge), forming the subsequent spacer layer on the conventional first spacer layer will result in an unpredictable and less robust profile of the second spacer layer. As the second spacer layer forms the mask for the resulting conductive gate regions, it is imperative that the profile of the second spacer layer be highly predictable, controllable and robust.